1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, and particularly to the arrangement of a source line contact CS of the nonvolatile semiconductor memory device.
2. Description of the Related Art
A NAND flash electrically erasable programmable read only memory (EEPROM) is known as a nonvolatile semiconductor memory device which is electrically rewritable and allows high integration. Each of the memory cell transistors of the NAND flash EEPROM each has a “stack gate structure” formed on a semiconductor substrate. The structure has a floating gate electrode layer, which is formed on an insulating film formed on a substrate and is provided for charge storing purpose, and a control gate electrode layer. Adjacent memory cell transistors are serially connected in series in the column direction, while having a common source or drain region, and select gate transistors are located at both ends of the serially-connected memory cell transistors, whereby a NAND cell unit is formed.
The NAND cell units are arrayed in a matrix to form a memory cell array. The NAND cell units, which are arrayed in the row, is called a NAND cell block. The gates of the select gate transistors arrayed in the same row are connected to the same select gate line. The control gates of the memory cell transistors arrayed in the same row are connected to the same control gate line.
Contacts for connecting the bit lines and the source lines are formed at both ends of the NAND cell unit in order to feed current to the individual NAND cell units. Two adjacent NAND cell units share one contact to reduce the contact occupying areas. Therefore, the NAND cell units are symmetrical with respect to the bit line contact and the source line contact. The bit line contact and the source line contact are formed between the select gate transistors of the adjacent NAND cell units.
The shorter-side size of the bit line contact between the active region and the bit line is the shortest in the NAND flash EEPROM. Accordingly, the longer-side size of the bit line contact needs to be long. For this reason, the interval between the select gate lines by the bit line contact needs to be wide enough to keep the select gate lines from contacting the bit line contact.
Meanwhile, source line contacts do not need to be insulated from each other unlike the bit line contacts and hence, the space between the select gate lines can be reduced.
A structure of the NAND flash memory in which the source line contacts CS formed on the active regions are alternately shifted in their array is already disclosed (e.g., Jpn. Pat. Appln. KOKAI Publication No. 10-189919).